In this paper, an enhanced self-checking Carry select adder (CSeA) architecture is introduced. However, we first show that the Carry select adder design presented literature does not have the self-checking property in all of its parts in spite of the stated claim. Then, we present a corrected design with the self-checking property that requires more overheads. In addition, we reveal some mistakes in reporting the transistor count of the proposed design in the literature in different sizes, and correct them which again leads to more transistor count and overhead. At the end, due to the fact that the performance of a CSeA depends on its grouping structure, the area overheads of different CSeAs including the corrected designs and the best of previous self-checking designs will be evaluated with respect to the same-size and different-size grouping structures. These evaluations show the comparison of different CSeAs, more appropriate compared to the previous evaluations.

adders, as one of the major components of digital computing systems, have a strong influence on their performance. There are various types of adders, each of which uses a different algorithm to do addition with a certain delay. In addition to low computational delay, minimizing power consumption is also a main priority in an adder circuit design. In this paper, the proposed adder is divided into several sub-blocks, and the circuit of each sub-block is designed based on multiplexers and NOR gates to calculate the output Carry or input Carry of the next sub-block. This method reduces the critical path delay, and therefore, increases the speed of the adder. Simulation and synthesis of the proposed adder is done for cases of 8, 16, 32, and 64 bits, and the results obtained are compared with those of the other fast adders. The synthesis results show that the proposed 16-and 32-bit adders have the lowest computation delay and also the best power delay product among all the recent popular adders.

Design of low-cost and high-speed datapath is very important for current computing systems. The adders are the essential parts of datapaths in computing systems. Among different types of adders, the Carry select adder (CSeA) has a high speed while having the area overhead, as well. A factor influencing the speed of this adder is the incorporated grouping structure dependent to its components' delay. In this paper, at first, the delay and area of different existing CSeA architectures are reduced by utilizing a fast and small multiplexer. Then, a new grouping structure is proposed for more delay reduction based on a delay analysis. Implementation and experimental results show that applying the proposed grouping and modifications on different CSeA architectures leads to a high delay reduction in the add operation compared to the best existing grouping structure. For example, the amount of delay reduction in the investigated 32-bit CSeA architectures is more than 33%. In addition, the average reduction of power-delay-product criterion for 32-bit and 64-bit CSeAs utilizing the proposed grouping equals45% and 35%, respectively, compared to the CSeAs incorporating the current best grouping.

The purpose of this paper is to design a 64×64 bit low power, low delay and high speed Arithmetic Logic Unit (ALU). Arithmetic Logic Unit performs arithmetic operation like addition, multiplication. adders play important role in ALU. For designing adder, the combination of Carry lookahead adder and Carry select adder, also add-one circuit have been used to achieve high speed and low area. In multiplier design, Booth algorithm and Wallace tree structure have been used. The proposed multiplier is based on Pipeline technique. In Wallace structure, compressors are used for partial product accumulation. By use of booth algorithm to generate partial product, speed of pipeline multiplier has been improved. Achieved delay and power consumption for 64 bit adder under supply voltage of 1. 3V and 2GHz frequency are 112ps and 12mw, respectively and for multiplier, delay and power consumption are 291ps and 950mw. The presented structures have been implemented in TSMC 130nm CMOS technology.

adders are among the most practical and useful circuits in microprocessors. They could also be used in other arithmetic operators. Traditionally, they are fabricated using CMOS technology. However, CMOS has faced some challenges in the nanoscale regime such as reduced gate controllability and high leakage currents. In contrast, Quantum Cellular Automata (QCA) is a promising alternative for the challenges of the next generation digital circuits. Based on QCA idea, in this paper a Carry-Skip adder (CSA) is designed, which as far as investigated, has not been previously presented in related works. As CSA adders are generally faster than ripple ones, our simulation results also confirm that the proposed CSA outperforms the state-of-the-art ripple and Carry lookahead adders and produces the result three QCA clock cycles faster even in the worst-case scenario. In addition, the proposed QCA adder outperforms its CMOS counterpart in terms of speed and power consumption.

The need for low-power VLSI chips is ignited by the enhanced market requirement for battery-powered end-user electronics, high-performance computing systems, and environmental concerns. The continuous advancement of the computational units found in applications such as digital signal processing, image processing, and high-performance CPUs has led to an indispensable demand for power-efficient, high-speed and compact multipliers. To address those low-power computational aspects with improved performance, an approach to design the multiplier using the algorithms of Vedic math is developed in this research. In the proposed work, the pre-computation technique is incorporated that aided in estimation of the carries during the partial product calculation stage; that enhanced the speed of the multiplier. This design was carried out using Cadence NCSIM 90 nm technology. The comparative analysis between the proposed multiplier design and the multipliers from the literature resulted in a substantial improvement in power dissipation as well as delay. The research was extended to assess the designed architectures’ performance statistically, applying the independent sample t-test hypothesis.

In this paper, a new hybrid low-power and area efficient Carry Look-Ahead adder in CNFET technology based on the full-swing Gate Diffusion Input (GDI) technique is proposed. The proposed CLA design in GDI logic style, not only decreases the circuit area effectively but also decreases the power consumption and delay parameters as well. The proposed design is simulated in HSPICE using the CNFET model parameters. Finally, the simulation results justify a good improvement in the circuit performance parameters such as power consumption, delay, chip size area and power-delay product (PDP) for the proposed CLA circuit.

This paper proposes a new high speed low power algorithm for unsigned digital multiplier without pipeline which could be easily expanded to a wider number of bits. The blocks of multiplier works in parallel which significantly increase the speed of multiplier. In proposed algorithm, the input bits of multiplier, are divided into smaller groups of bits which multiplication of these groups are in parallel and simultaneously. This division continues until the minimum number of input bits which is 2×2. In calculating the product of each category, the proposed algorithm is used, which leads to acceleration of the product of each category. The final result will be obtained from the sum of these smaller categories. Modified tree adder have been used to add smaller groups, which can increase the multiplication speed. Multipliers with input bit lengths of 64, 32, 16, 8, 4, and 2 have been implemented using the proposed algorithm in 180 nm and 90 nm technology, which its delay and power consumption with bit length of 32 in 180 nm are 3. 05 ns and 40 mW respectively. In 90 nm technology and with the 32 bit length the delay is 1. 53 nm and power consumption is 9. 7 mW. Also, using the proposed method, it is estimated that the delay of 128×128 bits multiplier in the 180 nm and 90 nm technology are equal to 5. 4ns and 2. 5ns, respectively. According to the results and in comparison with other works reported in the articles and in the same process, without increasing the power consumption and with a silicon area of 1. 5 times, the proposed multiplication speed has increased more than 2 times.

In special purpose circuits, the amount of energy consumed and the speed of operation are the main challenges. There are wide researches and methods to improve the performance of these types of circuits. One of these methods is to use a Residue Number System (RNS). In the RNS, there are a number of modules (channels) as a set to represent the number and perform parallel arithmetic operations. The most famous set is the 3-modlui set {2n-1, 2n, 2n +1}. The form of modules to the power of 2 makes it easier to perform binary computational operations. To use this system, you need to perform conversion operations from binary to residue (forward conversion) and residue to binary (reverse conversion). The greater the number of modules (channels) in the set, the higher the degree of parallelism of computational operations. In contrast, more complex forward and reverse conversion circuits are required. The overhead of conversion computing can reduce the efficiency of using this system, unless the number of consecutive operations is large enough to cover the conversion overhead time. In this paper, based on 3-moduli set {2n-1, 2n, 2n +1} evaluation, it was determined that for how many consecutive addition or multiplication operations, the use of RNS operations leads to greater speed. In this paper, we evaluate the Carry propagation adder as the most popular adder and parallel prefix adder as the high speed adder. Also, the parallel block multiplier circuit was used to evaluate the multiplication operations. First, modular adder/multiplier, binary, and forward and reverse conversion circuits were implemented and synthesized. We used Synopsys Design Compiler, K-2015. 06 version and 45nm technology. The results show that if the Carry propagation adder is used, in modules with a width of more than 8 bits (n≥8), if the number of consecutive operations is at least 4, it will speed up the calculations. Likewise, in the multiplication operation and parallel prefix addition, the number of sequences is reduced to two.